//module :top
//module function:only used for simulation
//author:wataru
//2021.11.16
module ammodtest(
						input 		 clk,
						input 		 rst,
						output[7:0] INsignal,   //调制信号
						output[7:0] carrier,   //载波
						output[15:0] ammodOut, //已调波
						output[15:0] demod_rec_result,//整流输出的信号
						output[15:0] filter_out //滤波之后的信号
);


//signal_in
//wire[7:0] INsignal ;
wire[7:0] INsignal_temp;
wire[7:0] carrier_temp;
wire[15:0] ammodOut_temp;
modelsim_signal_generator signalIn(
	.clk(clk),
	.rst(rst),
	.signal(INsignal_temp)//unsigned

);
assign INsignal = INsignal_temp ;
//carrier
carrier_generator carrierGenerator(
	.clk(clk),
	.rst(rst),
	.carrier(carrier_temp)//unsigned
);
assign carrier = carrier_temp - 8'd127;
//ammod
mult multmod(
	.dataa({1'b0,INsignal[7:1]}),
	.datab(carrier),
	.result(ammodOut_temp)
	);
assign ammodOut = ammodOut_temp ;

//demod
demodTop mydemod(
		.clk(clk),
		.rst(rst),
		.signalInDemod(ammodOut),
		.rectificationResult(demod_rec_result),
		.result(filter_out)

);
endmodule